1. Field of the Invention
The present invention relates to a signal transmission circuit in which a data signal line is driven based on a logic data and a transmitted data signal is received. More particularly, the present invention relates to a signal transmission circuit in which cross talk noise from a signal line other than this data signal line is reduced and further increase of transmission speed of the data signal can be accomplished.
2. Description of the Related Art
In a conventional semiconductor integrated circuit, capacitive coupling between adjacent signal lines to each other becomes strong with high density integration and formation of a fine wiring pattern. For this reason, cross talk noise due to the capacitive coupling has been a big problem in the operation of the semiconductor integrated circuit.
FIG. 1 is a circuit diagram illustrating the structure of a first conventional example of a general signal transmission circuit. In the first conventional example of the signal transmission circuit, a data signal line 1321 is driven by the drive inverter 1311 based on the data signal generated by a logic circuit 1301. The data signal is received by a receiver inverter 1312. Two data signal lines 1322 and 1323 are provided to be adjacent to the data signal line 1321. Therefore, the data signal line 1321 has a total parasitic capacitance composed of capacitances 1343 and 1344 between the data signal line 1321 and the two data signal lines 1322 and 1323, the gate capacitance 1341 of the receiver inverter 1312 and a capacitance 1342 between the data signal line 1321 and a ground line.
When the signal levels on two data signal lines 1322 and 1323 change, the data signal line 1321 undergoes the influence of cross talk noise in correspondence to a ratio of the parasitic capacitances 1343 and 1344 to the total parasitic capacitance. In other words, when the signal levels on the two data signal line 1322 and 1323 change, a signal level on the data signal line 1321 changes with the change of the signal levels on the signal lines 1322 and 1323, even if the signal line 1321 is driven to a predetermined level.
If the current drive ability of the drive inverter 1311 to the data signal line 1321 is not so sufficient that the level change of the signal level on the data signal line 1321 exceeds the logic threshold value of the receiver inverter 1312, the influence spreads to logic circuits subsequent to the receiver inverter 1312. As a result, a reception system (not shown) operates erroneously.
Also, the signals on the two data signal line 1322 and 1323 change into the direction opposite to that of the change of the signal on the data signal line 1321. In this case, the changes of the signals on the data signal lines 1322 and 1323 influence to the signal on the data signal line 1321 to delay the signal transmission on the data signal line 1321. Therefore, any measures are required to reduce the influence of the cross talk noise as described above.
FIG. 2 is a circuit diagram illustrating the structure of a second conventional example of the signal transmission circuit in which a measure adopting shield lines is taken. In the second conventional example of the signal transmission circuit, two shield lines 1431 and 1432 which are connected to the ground line are provided between each of the two data signal lines 1422 and 1423 and the data signal line 1421. As a result, the capacitive coupling between the data signal line 1421 and each of the two data signal lines 1422 and 1423 is blocked off.
As such a conventional example, a data bus structure of the semiconductor memory device which is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 5-151776) is known. In this data bus structure, the shield lines are provided on both sides of complementary data bus lines in parallel. The shield lines are connected to a power supply line or a ground line of a differential data amplifier which is connected to the data bus lines. Accordingly, even if cross talk noise is generated on the data bus lines via the shield lines because of the signal level change on another data signal line around the shield line, the differential data amplifier does not operate erroneously. This is because the cross talk noise acts as in-phase noise on the complementary data bus lines.
Besides, as such a conventional example, the semiconductor integrated circuit device which is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 3-224261) is known. In the semiconductor integrated circuit device, for the purpose that noise endurance can be increased without decreasing the size precision of the data signal line, one or more lines are provided on one or both sides of a plurality of signal lines for transmitting in-phase signals, in parallel. The one or more lines are set in a floating state.
However, when these conventional examples of the signal transmission circuit are applied to a semiconductor integrated circuit to eliminate the influence of cross talk noise while maintaining the speeding-up of transmission speed and the integration of the semiconductor integrated circuit, there are the following problems.
That is, there is the possibility that the erroneous operation of the circuit and the delay of signal transmission can be avoided in a specific noise mode which depends on the pattern of the cross talk noise in any conventional examples. However, as the first problem, because the capacitance between the signal line and the shield line finally increases a signal line load, the delay of the average signal transmission increases from the viewpoint of the total operation speed.
As the second problem, in order to suppress increase of the signal line load based on of the capacitance between the shield line and the signal line, it is necessary to provide a space between the signal line and the shield line in either of conventional examples. Therefore, an extra substrate area is required for the shield lines, resulting in increase of the area overhead of the shield lines.